With the continuous development of semiconductor technology, such as incorporating high-k dielectrics in the gate stack, strain engineering, pocket implants and optimization in materials and device structures, etc., the critical dimension of semiconductor devices has become smaller and smaller. However, when the critical dimension of the semiconductor devices is further reduced, the scaling of planar devices is proven to be extremely challenging due to degrading short channel effects, process variations and reliability degradation, etc. Comparing with the planar transistors, Fin field-effect transistors (FinFETs) have fully depleted fins, reduced random dopant fluctuation, improved mobility, lower parasitic junction capacitance and improved area efficiency, etc. Thus, FinFETs have attracted more and more attentions.
During the fabrication of integrated circuits (ICs), after forming semiconductor devices on a substrate, a plurality of metalized layers are formed to connect the semiconductor devices to circuits. The metalized layers include interconnect lines and conductive vias formed in contact through-holes, etc. The conductive vias formed in the contact through-holes are connected with the semiconductor devices; and the interconnect lines are connected with the conductive vias that are connected with the semiconductor devices to form circuits. The contact through-holes include the contact through-holes on surfaces of gate structures and contact through-holes connecting with active regions. With the continuous shrinking of the technical node of the ICs, the distance between adjacent gate structures has become smaller and smaller, especially for FinFETs, it is difficult to directly form contact through-holes on surfaces of the active regions between adjacent gate structures by a direct photolithography and etching process. Thus, a self-aligned contact through-hole (SAC) process has been used to form the contact through-holes connecting with the active regions.
During the fabrication process of the semiconductor structures, it is easy for the size of the contact through-holes formed by the existing SAC process to have differences with the designed value. Thus, the connecting performance of the metal contact vias is affected; and the performance of the semiconductor structure having such metal contact vias is also affected. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.